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1 lt1956/lt1956-5 1956f high voltage, 1.5a, 500khz step-down switching regulators n wide input range: 5.5v to 60v n 1.5a peak switch current n small 16-pin ssop or thermally enhanced tssop package n saturating switch design: 0.2 w n peak switch current maintained over full duty cycle range n constant 500khz switching frequency n effective supply current: 2.5ma n shutdown current: 25 m a n 1.2v feedback reference (lt1956) n 5v fixed output (lt1956-5) n easily synchronizable n cycle-by-cycle current limiting the lt ? 1956/lt1956-5 are 500khz monolithic buck switching regulators with an input voltage capability up to 60v. a high efficiency 1.5a, 0.2 w switch is included on the die along with all the necessary oscillator, control and logic circuitry. a current mode architecture provides fast tran- sient response and good loop stability. special design techniques and a new high voltage process achieve high efficiency over a wide input range. efficiency is maintained over a wide output current range by using the output to bias the circuitry and by utilizing a supply boost capacitor to saturate the power switch. patented circuitry maintains peak switch current over the full duty cycle range*. a shutdown pin reduces supply current to 25 m a and the device can be externally synchronized from 580khz to 700khz with a logic level input. the lt1956 /lt1956-5 are available in fused-lead 16-pin ssop and thermally enhanced tssop packages. n high voltage, industrial and automotive n portable computers n battery-powered systems n battery chargers n distributed power systems , ltc and lt are registered trademarks of linear technology corporation. 5v buck converter efficiency vs load current boost v in 6 2 10 12 10mq060n v out 5v 1a 4 15 14 11 220pf 4700pf ? united chemi-con thcs50eza225zt 1, 8, 9, 16 lt1956-5 shdn sync sw bias fb v c gnd 0.1 f 22 f 6.3v ceramic 10 h mmsd914ti 1956 ta01 2.2 f ? 100v ceramic v in 12v (transients to 60v) 4.7k load current (a) 0 efficiency (%) 80 90 100 1.00 1956 ta02 70 60 50 0.25 0.50 0.75 1.25 v out = 5v v out = 3.3v v in = 12v l = 18 h descriptio u features applicatio s u typical applicatio u *u.s. patent no. 6,498,466
2 lt1956/lt1956-5 1956f input voltage (v in ) ................................................. 60v boost pin above sw ............................................ 35v boost pin voltage ................................................. 68v sync, sense voltage (lt1956-5) ........................... 7v shdn voltage ........................................................... 6v bias pin voltage .................................................... 30v fb pin voltage/current (lt1956) ................... 3.5v/2ma order part number lt1956egn lt1956ign lt1956egn-5 lt1956ign-5 gn part marking 1956 1956i 19565 1956i5 t jmax = 125 c, q ja = 85 c/ w, q jc (pin 8) = 25 c/ w four corner pins soldered to ground plane absolute axi u rati gs w ww u package/order i for atio uu w gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 gnd sw nc v in nc boost nc gnd gnd shdn sync nc fb/sense v c bias gnd operating junction temperature range lt1956efe/lt1956efe-5/lt1956egn/lt1956egn-5 (notes 8, 10) ..................................... C 40 c to 125 c lt1956ife/lt1956ife-5/lt1956ign/lt1956ign-5 (notes 8, 10) ..................................... C 40 c to 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c (note 1) order part number lt1956efe lt1956ife lt1956efe-5 lt1956ife-5 fe part marking t jmax = 125 c, q ja = 45 c/ w, q jc (pad) = 10 c/ w exposed backside must be soldered to ground plane fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 gnd sw nc v in nc boost nc gnd gnd shdn sync nc fb/sense v c bias gnd consult ltc marketing for parts specified with wider operating temperature ranges. parameter conditions min typ max units reference voltage (lt1956) 5.5v v in 60v 1.204 1.219 1.234 v v ol + 0.2 v c v oh C 0.2 l 1.195 1.243 v sense voltage (lt1956-5) 5.5v v in 60v 4.94 5 5.06 v v ol + 0.2 v c v oh C 0.2 l 4.90 5.10 v sense pin resistance (lt1956-5) 9.5 13.8 19 k w fb input bias current (lt1956) l 0.5 1.5 m a error amp voltage gain (notes 2, 9) 200 400 v/v error amp g m dl (v c ) = 10 m a (note 9) 1500 2000 3000 m mho l 1000 3200 m mho v c to switch g m 1.7 a/v ea source current fb = 1v or v sense = 4.1v l 125 225 400 m a ea sink current fb = 1.4v or v sense = 5.7v l 100 225 450 m a v c switching threshold duty cycle = 0 0.9 v v c high clamp shdn = 1v 2.1 v the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t j = 25 c. v in = 15v, v c = 1.5v, shdn = 1v, boost o/c, sw o/c, unless otherwise noted. electrical characteristics 1956efe 1956ife 1956efe-5 1956ife-5
3 lt1956/lt1956-5 1956f parameter conditions min typ max units switch current limit v c open, boost = v in + 5v, fb = 1v or v sense = 4.1v l 1.5 2 3 a switch on resistance i sw = 1.5a, boost = v in + 5v (note 7) 0.2 0.3 w l 0.4 w maximum switch duty cycle fb = 1v or v sense = 4.1v 82 90 % l 75 90 % switch frequency v c set to give dc = 50% 460 500 540 khz l 430 570 khz f sw line regulation 5.5v v in 60v l 0.05 0.15 %/v f sw shifting threshold df = 10khz 0.8 v minimum input voltage (note 3) l 4.6 5.5 v minimum boost voltage (note 4) i sw 1.5a l 23 v boost current (note 5) boost = v in + 5v, i sw = 0.5a l 12 25 ma boost = v in + 5v, i sw = 1.5a l 42 70 ma input supply current (i vin ) (note 6) v bias = 5v 1.4 2.2 ma output supply current (i bias ) (note 6) v bias = 5v 2.9 4.2 ma shutdown supply current shdn = 0v, v in 60v, sw = 0v, v c open 25 75 m a l 200 m a lockout threshold v c open l 2.30 2.42 2.53 v shutdown thresholds v c open, shutting down l 0.15 0.37 0.6 v v c open, starting up l 0.25 0.45 0.6 v minimum sync amplitude l 1.5 2.2 v sync frequency range 580 700 khz sync input resistance 20 k w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t j = 25 c. v in = 15v, v c = 1.5v, shdn = 1v, boost o/c, sw o/c, unless otherwise noted. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: gain is measured with a v c swing equal to 200mv above the low clamp level to 200mv below the upper clamp level. note 3: minimum input voltage is not measured directly, but is guaranteed by other tests. it is defined as the voltage where internal bias lines are still regulated so that the reference voltage and oscillator remain constant. actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. see applications information. note 4: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 5: boost current is the current flowing into the boost pin with the pin held 5v above input voltage. it flows only during switch on time. note 6: input supply current is the quiescent current drawn by the input pin when the bias pin is held at 5v with switching disabled. bias supply current is the current drawn by the bias pin when the bias pin is held at 5v. total input referred supply current is calculated by summing input supply current (i vin ) with a fraction of supply current (i bias ): i total = i vin + (i bias )(v out /v in ) with v in = 15v, v out = 5v, i vin = 1.4ma, i bias = 2.9ma, i total = 2.4ma. note 7: switch on resistance is calculated by dividing v in to sw voltage by the forced current (1.5a). see typical performance characteristics for the graph of switch voltage at other currents. note 8: the lt1956efe/lt1956efe-5/lt1956egn/lt1956egn-5 are guaranteed to meet performance specifications from 0 c to 125 c junction temperature. specifications over the C40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt1956ife/lt1956ife-5/ lt1956ign/lt1956ign-5 are guaranteed over the full C 40 c to 125 c operating junction temperature range. note 9: transconductance and voltage gain refer to the internal amplifier exclusive of the voltage divider. to calculate gain and transconductance, refer to the sense pin on fixed voltage parts. divide values shown by the ratio v out /1.219. note 10: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability.
4 lt1956/lt1956-5 1956f switch peak current limit shdn pin bias current shutdown supply current lockout and shutdown thresholds shutdown supply current error amplifier transconductance fb pin voltage and current error amplifier transconductance frequency foldback typical perfor a ce characteristics uw duty cycle (%) 1.0 switch peak current (a) 1.5 2.0 2.5 20 40 typical 60 80 1956 g01 100 0 guaranteed minimum junction temperature ( c) ?0 feedback voltage (v) current ( a) 1.224 1.229 1.234 25 75 1956 g02 1.219 1.214 ?5 0 50 100 125 1.209 1.204 1.5 2.0 1.0 0.5 0 voltage current junction temperature ( c) ?0 250 200 150 100 12 6 0 25 75 1956 g03 ?5 0 50 100 125 current ( m a) current required to force shutdown (flows out of pin). after shutdown, current drops to a few m a at 2.38v standby threshold (current flows out of pin) junction temperature ( c) ?0 shdn pin voltage (v) 50 100 1956 g04 0 25 75 2.4 2.0 1.6 1.2 0.8 0.4 0 25 125 lockout start-up shutdown input voltage (v) 0 input supply current ( a) 1956 g05 10 20 30 40 50 60 40 35 30 25 20 15 10 5 0 v shdn = 0v shutdown voltage (v) 0 0 input supply current ( a) 50 100 150 200 250 300 0.1 0.2 0.3 0.4 1956 g06 0.5 v in = 60v v in = 15v junction temperature transconductance ( mho) 1956 g07 2500 2000 1500 1000 500 0 ?0 50 100 0 25 75 25 125 frequency (hz) gain ( m mho) phase (deg) 3000 2500 2000 1500 1000 500 200 150 100 50 0 ?0 100 10k 100k 10m 1956 g08 1k 1m gain phase error amplifier equivalent circuit r out 200k c out 12pf v c r load = 50 w v fb 2 10 ? ) ( v fb (v) 0 0.2 switiching frequency (khz) or fb current ( a) 375 500 625 1.0 1956 g09 250 125 0 0.4 0.6 0.8 1.2 switching frequency fb pin current
5 lt1956/lt1956-5 1956f switching frequency boost pin current v c pin shutdown threshold minimum input voltage with 5v output switch voltage drop typical perfor a ce characteristics uw junction temperature ( c) ?0 frequency (khz) 50 100 1956 g10 0 25 75 575 550 525 500 475 450 425 25 125 load current (a) 0 input voltage (v) 1956 g11 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 7.5 7.0 6.5 6.0 5.5 5.0 minimum input voltage to start minimum input voltage to run v out = 5v l = 18 h switch current (a) 0 0.5 1 1.5 boost pin current (ma) 1956 g12 45 40 35 30 25 20 15 10 5 0 junction temperature ( c) ?0 1.5 1.7 2.1 25 75 1956 g13 1.3 1.1 ?5 0 50 100 125 0.9 0.7 1.9 threshold voltage (v) switch current (a) 0 0.5 1 1.5 switch voltage (mv) 1766 g14 450 400 350 300 250 200 150 100 50 0 t j = 125 c t j = 25 c t j = 40 c junction temperature ( c) ?0 switch minimum on time (ns) 50 100 1956 g15 0 25 75 600 500 400 300 200 100 0 25 125 switch minimum on time vs temperature
6 lt1956/lt1956-5 1956f v c (pin 11) the v c pin is the output of the error amplifier and the input of the peak switch current comparator. it is normally used for frequency compensation, but can also serve as a current clamp or control loop override. v c sits at about 1v for light loads and 2v at maximum load. it can be driven to ground to shut off the regulator, but if driven high, current must be limited to 4ma. fb/sense (pin 12): the feedback pin is used to set the output voltage using an external voltage divider that gen- erates 1.22v at the pin for the desired output voltage. the 5v fixed output voltage parts have the divider included on the chip and the fb pin is used as a sense pin, connected directly to the 5v output. three additional functions are performed by the fb pin. when the pin voltage drops below 0.6v, switch current limit is reduced and the exter- nal sync function is disabled. below 0.8v, switching frequency is also reduced. see feedback pin functions in applications information for details. sync (pin 14): the sync pin is used to synchronize the internal oscillator to an external signal. it is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. the synchronizing range is equal to initial operating frequency up to 700khz. see synchronizing in applications information for details. if unused, this pin should be tied to ground. shdn (pin 15): the shdn pin is used to turn off the regulator and to reduce input current to a few microam- peres. this pin has two thresholds: one at 2.38v to disable switching and a second at 0.4v to force complete mi- cropower shutdown. the 2.38v threshold functions as an accurate undervoltage lockout (uvlo); sometimes used to prevent the regulator from delivering power until the input voltage has reached a predetermined level. if the shdn pin functions are not required, the pin can either be left open (to allow an internal bias current to lift the pin to a default high state) or be forced high to a level not to exceed 6v. gnd (pins 1, 8, 9, 16): the gnd pin connections act as the reference for the regulated output, so load regulation will suffer if the ground end of the load is not at the same voltage as the gnd pins of the ic. this condition will occur when load current or other currents flow through metal paths between the gnd pins and the load ground. keep the paths between the gnd pins and the load ground short and use a ground plane when possible. for the fe package, the exposed pad should be soldered to the copper gnd plane underneath the device. (see applications informa- tionlayout considerations.) sw (pin 2): the switch pin is the emitter of the on-chip power npn switch. this pin is driven up to the input pin voltage during switch on time. inductor current drives the switch pin negative during switch off time. negative volt- age is clamped with the external catch diode. maximum negative switch voltage allowed is C 0.8v. nc (pins 3, 5, 7, 13): no connection. v in (pin 4): this is the collector of the on-chip power npn switch. v in powers the internal control circuitry when a voltage on the bias pin is not present. high di/dt edges occur on this pin during switch turn on and off. keep the path short from the v in pin through the input bypass capacitor, through the catch diode back to sw. all trace inductance on this path will create a voltage spike at switch off, adding to the v ce voltage across the internal npn. boost (pin 6): the boost pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar npn power switch. without this added voltage, the typical switch voltage loss would be about 1.5v. the additional boost voltage allows the switch to saturate and voltage loss approximates that of a 0.2 w fet struc- ture, but with much smaller die area. bias (pin 10): the bias pin is used to improve efficiency when operating at higher input voltages and light load current. connecting this pin to the regulated output volt- age forces most of the internal circuitry to draw its oper- ating current from the output voltage rather than the input supply. this architecture increases efficiency especially when the input voltage is much higher than the output. minimum output voltage setting for this mode of operation is 3v. uu u pi fu ctio s
7 lt1956/lt1956-5 1956f it much easier to frequency compensate the feedback loop and also gives much quicker transient response. most of the circuitry of the lt1956 operates from an internal 2.9v bias line. the bias regulator normally draws power from the regulator input pin, but if the bias pin is connected to an external voltage higher than 3v, bias power will be drawn from the external source (typically the regulated output voltage). this will improve efficiency if the bias pin voltage is lower than regulator input voltage. high switch efficiency is attained by using the boost pin to provide a voltage to the switch driver which is higher than the input voltage, allowing switch to be saturated. this boosted voltage is generated with an external capaci- tor and diode. two comparators are connected to the shutdown pin. one has a 2.38v threshold for undervoltage lockout and the second has a 0.4v threshold for complete shutdown. the lt1956 is a constant frequency, current mode buck converter. this means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. in addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. a switch cycle starts with an oscilla- tor pulse which sets the r s flip-flop to turn the switch on. when switch current reaches a level set by the inverting input of the comparator, the flip-flop is reset and the switch turns off. output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. this technique means that the error amplifier commands current to be delivered to the output rather than voltage. a voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180 shift will occur. the current fed system will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the lc resonant frequency. this makes block diagra w figure 1. lt1956 block diagram + + + + s v in 2.9v bias regulator 500khz oscillator frequency foldback sw fb gnd 1, 8, 9, 16 1956 f01 slope comp antislope comp bias internal v cc sync 0.4v 5.5 a current comparator r limit r sense error amplifier g m = 2000 m mho q2 foldback current limit clamp boost r s flip-flop driver circuitry s r q1 power switch 1.22v 4 10 14 shdn 15 6 2 12 11 v c lockout comparator shutdown comparator 2.38v 1 q3 v c(max) clamp
8 lt1956/lt1956-5 1956f current through the diode and inductor is equal to the short-circuit current limit of the switch (typically 2a for the lt1956, folding back to less than 1a). minimum switch on time limitations would prevent the switcher from attaining a sufficiently low duty cycle if switching frequency were maintained at 500khz, so frequency is reduced by about 5:1 when the feedback pin voltage drops below 0.8v (see frequency foldback graph). this does not affect operation with normal load conditions; one simply sees a shift in switching frequency during start-up as the output voltage rises. in addition to lower switching frequency, the lt1956 also operates at lower switch current limit when the feedback pin voltage drops below 0.6v. q2 in figure 2 performs this function by clamping the v c pin to a voltage less than its normal 2.1v upper clamp level. this foldback current limit greatly reduces power dissipation in the ic, diode and in- ductor during short-circuit conditions. external synchro- nization is also disabled to prevent interference with fold- back operation. again, it is nearly transparent to the user under normal load conditions. the only loads that may be affected are current source loads which maintain full load current with output voltage less than 50% of final value. in these rare situations the feedback pin can be clamped above 0.6v with an external diode to defeat foldback current limit. caution: clamping the feedback pin means that frequency shifting will also be defeated, so a combination of high in- put voltage and dead shorted output may cause the lt1956 to lose control of current limit. the internal circuitry which forces reduced switching frequency also causes current to flow out of the feedback pin when output voltage is low. the equivalent circuitry is shown in figure 2. q1 is completely off during normal operation. if the fb pin falls below 0.8v, q1 begins to conduct current and reduces frequency at the rate of approximately 3.5khz/ m a. to ensure adequate frequency foldback (under worst-case short-circuit conditions), the external divider thevinin resistance must be low enough to pull 115 m a out of the fb pin with 0.44v on the pin (r div 3.8k). the net result is that reductions in frequency and current limit are affected by output voltage divider imped- ance. although divider impedance is not critical, caution should be used if resistors are increased beyond the suggested values and short-circuit conditions will occur feedback pin functions the feedback (fb) pin on the lt1956 is used to set output voltage and provide several overload protection features. the first part of this section deals with selecting resistors to set output voltage and the remaining part talks about foldback frequency and current limiting created by the fb pin. please read both parts before committing to a final design. the 5v fixed output voltage part (lt1956-5) has internal divider resistors and the fb pin is renamed sense, connected directly to the output. the suggested value for the output divider resistor (see figure 2) from fb to ground (r2) is 5k or less, and a formula for r1 is shown below. the output voltage error caused by ignoring the input bias current on the fb pin is less than 0.25% with r2 = 5k. a table of standard 1% values is shown in table 1 for common output voltages. please read the following section if divider resistors are increased above the suggested values. r rv out 1 2122 122 = - () . . table 1 output r1 % error at output voltage r2 (nearest 1%) due to discrete 1% (v) (k w )(k w ) resistor steps 3 4.99 7.32 + 0.32 3.3 4.99 8.45 C 0.43 5 4.99 15.4 C 0.30 6 4.75 18.7 + 0.38 8 4.47 24.9 + 0.20 10 4.32 30.9 C 0.54 12 4.12 36.5 + 0.24 15 4.12 46.4 C 0.27 more than just voltage feedback the feedback pin is used for more than just output voltage sensing. it also reduces switching frequency and current limit when output voltage is very low (see the frequency foldback graph in typical performance characteristics). this is done to control power dissipation in both the ic and in the external diode and inductor during short-circuit conditions. a shorted output requires the switching regu- lator to operate at very low duty cycles, and the average applicatio s i for atio wu uu
9 lt1956/lt1956-5 1956f figure 2. frequency and current limit foldback with high input voltage. high frequency pickup will in- crease and the protection accorded by frequency and current foldback will decrease. choosing the inductor for most applications, the output inductor will fall into the range of 5 m h to 30 m h. lower values are chosen to reduce physical size of the inductor. higher values allow more output current because they reduce peak current seen by the lt1956 switch, which has a 1.5a limit. higher values also reduce output ripple voltage. when choosing an inductor you will need to consider output ripple voltage, maximum load current, peak induc- tor current and fault current in the inductor. in addition, other factors such as core and copper losses, allowable component height, emi, saturation and cost should also be considered. the following procedure is suggested as a way of handling these somewhat complicated and con- flicting requirements. output ripple voltage figure 3 shows a comparison of output ripple voltage for the lt1956 using either a tantalum or ceramic output capacitor. it can be seen from figure 3 that output ripple voltage can be significantly reduced by using the ceramic output capacitor; the significant decrease in output ripple voltage is due to the very low esr of ceramic capacitors. + 1.2v buffer v sw l1 v c gnd to sync circuit 1956 f02 to frequency shifting r3 1k r4 2k r1 c1 r2 output 5v error amplifier fb 1.4v q1 lt1956 q2 + applicatio s i for atio wu uu output ripple voltage is determined by ripple current (i lp-p ) through the inductor and the high frequency impedance of the output capacitor. at high frequencies, the impedance of the tantalum capacitor is dominated by its effective series resistance (esr). tantalum output capacitor the typical method for reducing output ripple voltage when using a tantalum output capacitor is to increase the inductor value (to reduce the ripple current in the induc- tor). the following equations will help in choosing the required inductor value to achieve a desirable output ripple voltage level. if output ripple voltage is of less importance, the subsequent suggestions in peak inductor and fault current and emi will additionally help in the selection of the inductor value. figure 3. lt1956 output ripple voltage waveforms. ceramic vs tantalum output capacitors 1 s/div 10mv/div v out using 22 f ceramic output capacitor v out using 100 f, 0.08 tantalum output capacitor 10mv/div v in = 12v v out = 5v l = 15 h 1956 f03
10 lt1956/lt1956-5 1956f applicatio s i for atio wu uu peak-to-peak output ripple voltage is the sum of a triwave (created by peak-to-peak ripple current (i lp-p ) times esr) and a square wave (created by parasitic inductance (esl) and ripple current slew rate). capacitive reactance is assumed to be small compared to esr or esl. v i esr esl di dt ripple lp p = ()() + () - s where: esr = equivalent series resistance of the output capacitor esl = equivalent series inductance of the output capacitor di/dt = slew rate of inductor ripple current = v in /l peak-to-peak ripple current (i lp-p ) through the inductor and into the output capacitor is typically chosen to be between 20% and 40% of the maximum load current. it is approximated by: i vvv vfl lp p out in out in - = ()( ) ()()() example: with v in = 12v, v out = 5v, l = 15 m h, esr = 0.080 w and esl = 10nh, output ripple voltage can be approximated as follows: ia di dt v mv ripple lp-p p-p = () - () () ()( ) = == = ()() + ()() () =+ = - - 512 5 12 15 10 500 10 0 389 12 15 10 10 0 8 0 389 0 08 10 10 10 0 8 0 031 0 008 39 66 6 6 96 . . .. . .. s to reduce output ripple voltage further requires an in- crease in the inductor value with the trade-off being a physically larger inductor with the possibility of increased component height and cost. ceramic output capacitor an alternative way to further reduce output ripple voltage is to reduce the esr of the output capacitor by using a ceramic capacitor. although this reduction of esr re- moves a useful zero in the overall loop response, this zero can be replaced by inserting a resistor (r c ) in series with the v c pin and the compensation capacitor c c . (see ceramic capacitors in applications information.) peak inductor current and fault current to ensure that the inductor will not saturate, the peak in- ductor current should be calculated knowing the maximum load current. an appropriate inductor should then be cho- sen. in addition, a decision should be made whether or not the inductor must withstand continuous fault conditions. if maximum load current is 0.5a, for instance, a 0.5a inductor may not survive a continuous 2a overload condi- tion. dead shorts will actually be more gentle on the inductor because the lt1956 has frequency and current limit foldback. peak inductor and switch current can be significantly higher than output current, especially with smaller induc- tors and lighter loads, so dont omit this step. powdered table 2 vendor/ value i dc(max) dcr height part no. ( m h) (amps) (ohms) (mm) coiltronics up1b-100 10 1.9 0.111 5.0 up1b-220 22 1.2 0.254 5.0 up2b-220 22 2.0 0.062 6.0 up2b-330 33 1.7 0.092 6.0 up1b-150 15 1.5 0.175 5.0 coilcraft d01813p-153hc 15 1.5 0.170 5.0 d01813p-103hc 10 1.9 0.111 5.0 d53316p-223 22 1.6 0.207 5.1 d53316p-333 33 1.4 0.334 5.1 lp025060b-682 6.8 1.3 0.165 1.65 sumida cdrh4d28-4r7 4.7 1.32 0.072 3.0 cdrh5d28-100 10 1.30 0.065 3.0 cdrh6d28-150 15 1.40 0.084 3.0 cdrh6d28-180 18 1.32 0.095 3.0 cdrh6d28-220 22 1.20 0.128 3.0 cdrh6d38-220 22 1.30 0.096 4.0
11 lt1956/lt1956-5 1956f applicatio s i for atio wu uu iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. other core mate- rials fall somewhere in between. the following formula assumes continuous mode of operation, but errs only slightly on the high side for discontinuous mode, so it can be used for all conditions. ii i i vvv vfl peak out lp p out out in out in =+ =+ () - 22 emi decide if the design can tolerate an open core geometry like a rod or barrel, which have high magnetic field radiation, or whether it needs a closed core like a toroid to prevent emi problems. this is a tough decision because the rods or barrels are temptingly cheap and small and there are no helpful guidelines to calculate when the magnetic field radiation will be a problem. additional considerations after making an initial choice, consider additional factors such as core losses and second sourcing, etc. use the experts in linear technologys applications department if you feel uncertain about the final choice. they have experience with a wide range of inductor types and can tell you about the latest developments in low profile, surface mounting, etc. maximum output load current maximum load current for a buck converter is limited by the maximum switch current rating (i p ). the current rating for the lt1956 is 1.5a. unlike most current mode convert- ers, the lt1956 maximum switch current limit does not fall off at high duty cycles. most current mode converters suffer a drop off of peak switch current for duty cycles above 50%. this is due to the effects of slope compensa- tion required to prevent subharmonic oscillations in cur- rent mode converters. (for detailed analysis, see applica- tion note 19.) the lt1956 is able to maintain peak switch current limit over the full duty cycle range by using patented circuitry to cancel the effects of slope compensation on peak switch current without affecting the frequency compensation it provides. maximum load current would be equal to maximum switch current for an infinitely large inductor, but with finite inductor size, maximum load current is reduced by one half of peak-to-peak inductor current (i lp-p ). the following formula assumes continuous mode operation, implying that the term on the right is less than one half of i p . i continuous mode i i i vvvvv vfl out max p lp p p out f in out f in () == + ()( ) ()( )()() - 22 for v out = 5v, v in(max) = 8v, v f(di) = 0.63v, f = 500khz and l = 10 m h: i a out max () . .. .. . = + ()( ) ()() ()() == 15 5 0 63 8 5 0 63 2 8 500 10 10 10 15 017 133 36 note that there is less load current available at the higher input voltage because inductor ripple current increases. at v in = 15v and using the same set of conditions: i a out max () . .. .. . = + ()( ) ()( ) ()() == 15 5 0 63 15 5 0 63 2 15 500 10 10 10 15 035 115 36 to calculate peak switch current with a given set of conditions, use: ii i i vvvvv vfl sw peak out lp p out out f in out f in () =+ =+ + ()( ) ()( )()() - 2 2 reduced inductor value and discontinuous mode if the smallest inductor value is of the most importance to a converter design, in order to reduce inductor size/cost, discontinuous mode may yield the smallest inductor
12 lt1956/lt1956-5 1956f applicatio s i for atio wu uu load current is required, the inductor value must be increased. if i out(max) no longer meets the discontinuous mode criteria, use the i out(max) equation for continuous mode; the lt1956 is designed to operate well in both modes of operation, allowing a large range of inductor values to be used. short-circuit considerations for a ground short-circuit fault on the regulated output, the maximum input voltage for the lt1956 is typically limited to 25v. if a greater input voltage is required, increasing the resistance in series with the inductor may suffice (see short-circuit calculations at the end of this section). alternatively, the 1.5a lt1766 can be used since it is identical to the lt1956 but runs at a lower frequency of 200khz, allowing higher sustained input voltage capa- bility during output short circuit. the lt1956 is a current mode controller. it uses the v c node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as peak switch current is reached. the internal clamp on the v c node, nominally 2v, then acts as an output switch peak current limit. this action becomes the switch current limit specification. the maximum available output power is then determined by the switch current limit. a potential controllability problem could occur under short-circuit conditions. if the power supply output is short circuited, the feedback amplifier responds to the low output voltage by raising the control voltage, v c , to its peak current limit value. ideally, the output switch would be turned on, and then turned off as its current exceeded the value indicated by v c . however, there is finite response time involved in both the current comparator and turnoff of the output switch. these result in a minimum on time t on(min) . when combined with the large ratio of v in to (v f + i ? r), the diode forward voltage plus inductor i ? r voltage drop, the potential exists for a loss of control. expressed mathematically the requirement to maintain control is: ft vir v on f in + solu tion. the maximum output load current in discontinu- ous mode, however, must be calculated and is defined later in this section. discontinuous mode is entered when the output load current is less than one-half of the inductor ripple current (i lp-p ). in this mode, inductor current falls to zero before the next switch turn-on (see figure 8). buck converters will be in discontinuous mode for output load current given by: i discontinous mode vvvvv vfl out out f in out f in < + ()() ()( )()() 2 the inductor value in a buck converter is usually chosen large enough to keep inductor ripple current (i lp-p ) low; this is done to minimize output ripple voltage and maxi- mize output load current. in the case of large inductor values, as seen in the equation above, discontinuous mode will be associated with light loads. when choosing small inductor values, however, discon- tinuous mode will occur at much higher output load currents. the limit to the smallest inductor value that can be chosen is set by the lt1956 peak switch current (i p ) and the maximum output load current required given by: i out(max) lp-p discontinuous mode i i iflv vvvvv ppin out f in out f == +- 22 22 () ()()( ) ()( ) example: for v in = 15v, v out = 5v, v f = 0.63v, f = 500khz and l = 4 m h i discontinuous mode out max () . ( )( )( ) (.)(.) = + - 1 5 500 10 4 10 15 25063155063 236 i out(max) discontinuous mode = 0.639a what has been shown here is that if high inductor ripple current and discontinuous mode operation can be toler- ated, small inductor values can be used. if a higher output
13 lt1956/lt1956-5 1956f applicatio s i for atio wu uu where: f = switching frequency t on = switch minimum on time v f = diode forward voltage v in = input voltage i ? r = inductor i ? r voltage drop if this condition is not observed, the current will not be limited at i pk , but will cycle-by-cycle ratchet up to some higher value. using the nominal lt1956 clock frequency of 500khz, a v in of 12v and a (v f + i ? r) of say 0.7v, the maximum t on to maintain control would be approximately 116ns, an unacceptably short time. the solution to this dilemma is to slow down the oscillator when the fb pin voltage is abnormally low thereby indicat- ing some sort of short-circuit condition. oscillator fre- quency is unaffected until fb voltage drops to about 2/3 of its normal value. below this point the oscillator frequency decreases roughly linearly down to a limit of about 100khz. this lower oscillator frequency during short-circuit condi- tions can then maintain control with the effective mini- mum on time. even with frequency foldback, however, the lt1956 will not survive a permanent output short at the absolute maximum voltage rating of v in = 60v; this is defined solely by internal semiconductor junction break- down effects. for the maximum input voltage allowed during an output short to ground, the previous equation defining minimum on-time can be used. assuming v f (d1 catch diode) = 0.63v at 1a (short-circuit current is folded back to typical switch current limit ? 0.5), i (inductor) ? dcr = 1a ? 0.128 = 0.128v (l = cdrh6d28-22), typical f = 100khz (folded back) and typical minimum on-time = 300ns, the maxi- mum allowable input voltage during an output short to ground is typically: v in = (0.63v + 0.128v)/(100khz ? 300ns) v in(max) = 25v increasing the dcr of the inductor will increase the maxi- mum v in allowed during an output short to ground but will also drop overall efficiency during normal operation. every time the converter wakes up from shutdown or undervoltage lockout to begin switching, the output capacitor may potentially be starting from 0v. this re- quires that the part obey the overall duty cycle demanded by the loop, related to v in and v out , as the output voltage rises to its target value. it is recommended that for [v in / (v out + v f )] ratios > 4, a soft-start circuit should be used to control the output capacitor charge rate during start-up or during recovery from an output short circuit, thereby adding additional control over peak inductor current. see buck converter with adjustable soft-start later in this data sheet. output capacitor the lt1956 will operate with either ceramic or tantalum output capacitors. the output capacitor is normally cho- sen by its effective series resistance (esr), because this is what determines output ripple voltage. the esr range for typical lt1956 applications using a tantalum output capacitor is 0.05 w to 0.2 w . a typical output capacitor is an avx type tps, 100 m f at 10v, with a guaranteed esr less than 0.1 w . this is a d size surface mount solid tantalum capacitor. tps capacitors are specially constructed and tested for low esr, so they give the lowest esr for a given volume. the value in microfarads is not particularly criti- cal, and values from 22 m f to greater than 500 m f work well, but you cannot cheat mother nature on esr. if you find a tiny 22 m f solid tantalum capacitor, it will have high esr, and output ripple voltage will be terrible. table 3 shows some typical solid tantalum surface mount capacitors. table 3. surface mount solid tantalum capacitor esr and ripple current e case size esr (max, w ) ripple current (a) avx tps, sprague 593d 0.1 to 0.3 0.7 to 1.1 d case size avx tps, sprague 593d 0.1 to 0.3 0.7 to 1.1 c case size avx tps 0.2 (typ) 0.5 (typ) unlike the input capacitor, rms ripple current in the output capacitor is normally low enough that ripple cur- rent rating is not an issue. the current waveform is triangular with a typical value of 125ma rms . the formula to calculate this is:
14 lt1956/lt1956-5 1956f output capacitor ripple current (rms): i vvv lfv ripple rms out in out in () . = ()( ) ()()( ) 029 ceramic capacitors ceramic capacitors are generally chosen for their good high frequency operation, small size and very low esr (effective series resistance). their low esr reduces output ripple voltage but also removes a useful zero in the loop frequency response, common to tantalum capaci- tors. to compensate for this, a resistor r c can be placed in series with the v c compensation capacitor c c . care must be taken however, since this resistor sets the high frequency gain of the error amplifier, including the gain at the switching frequency. if the gain of the error amplifier is high enough at the switching frequency, output ripple voltage (although smaller for a ceramic output capacitor) may still affect the proper operation of the regulator. a filter capacitor c f in parallel with the r c /c c network is suggested to control possible ripple at the v c pin. the lt1956 can be stabilized for v out = 5v at 1a using a 22 m f ceramic output capacitor and v c com- ponent values of c c = 4700pf, r c = 4.7k and c f = 220pf. input capacitor step-down regulators draw current from the input supply in pulses. the rise and fall times of these pulses are very fast. the input capacitor is required to reduce the voltage ripple this causes at the input of lt1956 and force the switching current into a tight local loop, thereby minimiz- ing emi. the rms ripple current can be calculated from: ici vvv v ripple rms in out out in out in () = () 2 ceramic capacitors are ideal for input bypassing. at 500khz switching frequency, the energy storage requirement of the input capacitor suggests that values in the range of 2.2 m f to 10 m f are suitable for most applications. if opera- tion is required close to the minimum input required by the output of the lt1956, a larger value may be required. this is to prevent excessive ripple causing dips below the mini- mum operating voltage resulting in erratic operation. depending on how the lt1956 circuit is powered up you may need to check for input voltage transients. the input voltage transients may be caused by input voltage steps or by connecting the lt1956 converter to an already powered up source such as a wall adapter. the sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic inductance of the leads. this energy will cause the input voltage to swing above the dc level of input power source and it may exceed the maximum voltage rating of input capacitor and lt1956. the easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low esr input capacitor. the selected capacitor needs to have the right amount of esr in order to critically dampen the resonant circuit formed by the input lead inductance and the input capacitor. the typical values of esr will fall in the range of 0.5 w to 2 w and capacitance will fall in the range of 5 m f to 50 m f. if tantalum capacitors are used, values in the 22 m f to 470 m f range are generally needed to minimize esr and meet ripple current and surge ratings. care should be taken to ensure the ripple and surge ratings are not exceeded. the avx tps and kemet t495 series are surge rated. avx recommends derating capacitor operating voltage by 2 for high surge applications. catch diode highest efficiency operation requires the use of a schottky type diode. dc switching losses are minimized due to its low forward voltage drop, and ac behavior is benign due to its lack of a significant reverse recovery time. schottky diodes are generally available with reverse voltage ratings of up to 60v and even 100v, and are price competitive with other types. the use of so-called ultrafast recovery diodes is gener- ally not recommended. when operating in continuous mode, the reverse recovery time exhibited by ultrafast diodes will result in a slingshot type effect. the power applicatio s i for atio wu uu
15 lt1956/lt1956-5 1956f internal switch will ramp up v in current into the diode in an attempt to get it to recover. then, when the diode has finally turned off, some tens of nanoseconds later, the v sw node voltage ramps up at an extremely high dv/dt, per- haps 5 to even 10v/ns ! with real world lead inductances, the v sw node can easily overshoot the v in rail. this can result in poor rfi behavior and if the overshoot is severe enough, damage the ic itself. the suggested catch diode (d1) is an international recti- fier 10mq060n schottky. it is rated at 1.5a average forward current and 60v reverse voltage. typical forward voltage is 0.63v at 1a. the diode conducts current only during switch off time. peak reverse voltage is equal to regulator input voltage. average forward current in normal operation can be calculated from: i d(avg) = i out (1 C dc) this formula will not yield values higher than 1.5a with maximum load current of 1.5a. the only reason to consider a larger diode is the worst-case condition of a high input voltage and shorted output. with a shorted condition, diode current will increase to a typical value of 2a, determined by peak switch current limit. this is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continuous operation under these conditions must be tolerated. boost pin for most applications, the boost components are a 0.1 m f capacitor and an mmsd914ti diode. the anode is typi- cally connected to the regulated output voltage to generate a voltage approximately v out above v in to drive the output stage. however, the output stage discharges the boost capacitor during the on time of the switch. the output driver requires at least 3v of headroom throughout this period to keep the switch fully saturated. if the output voltage is less than 3v, it is recommended that an alternate boost supply is used. the boost diode can be connected to the input, although, care must be taken to prevent the 2 v in boost voltage from exceeding the boost pin absolute maximum rating. the additional voltage across the switch driver also increases power loss, reducing efficiency. if available, an independent supply can be used with a local bypass capacitor. a 0.1 m f boost capacitor is recommended for most appli- cations. almost any type of film or ceramic capacitor is suitable, but the esr should be <1 w to ensure it can be fully recharged during the off time of the switch. the capacitor value is derived from worst-case conditions of 1800ns on time, 42ma boost current and 0.7v discharge ripple. the boost capacitor value could be reduced under less demanding conditions, but this will not improve circuit operation or efficiency. under low input voltage and low load conditions, a higher value capacitor will reduce discharge ripple and improve start-up operation. shutdown function and undervoltage lockout figure 4 shows how to add undervoltage lockout (uvlo) to the lt1956. typically, uvlo is used in situations where the input supply is current limited , or has a relatively high source resistance. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where these problems might occur. threshold voltage for lockout is about 2.38v. a 5.5 m a bias current flows out of the pin at this threshold. the internally generated current is used to force a default high state on the shutdown pin if the pin is left open. when low shut- down current is not an issue, the error due to this current can be minimized by making r lo 10k or less. if shutdown current is an issue, r lo can be raised to 100k, but the error due to initial bias current and changes with temperature should be considered. rk r rv v vr a lo hi lo in lo = () = - () - () 10 238 238 55 to 100k 25k suggested . .. m v in = minimum input voltage keep the connections from the resistors to the shutdown pin short and make sure that interplane or surface capaci- tance to the switching nodes are minimized. if high resistor values are used, the shutdown pin should be applicatio s i for atio wu uu
16 lt1956/lt1956-5 1956f bypassed with a 1000pf capacitor to prevent coupling problems from the switch node. if hysteresis is desired in the undervoltage lockout point, a resistor r fb can be added to the output node. resistor values can be calcu- lated from: r rv vv v ra rrv v hi lo in out lo fb hi out = -+ () + [] - () = () () 238 1 238 55 ./ .. / dd d m 25k suggested for r lo v in = input voltage at which switching stops as input voltage descends to trip level d v = hysteresis in input voltage level example: output voltage is 5v, switching is to stop if input voltage drops below 12v and should not restart unless input rises back to 13.5v. d v is therefore 1.5v and v in = 12v. let r lo = 25k. r k ka k k rk k hi fb = -+ () + [] m () = () = = () = 25 12 2 38 1 5 5 1 1 5 238 25 55 25 10 41 224 116 116 5 1 5 387 ../ . . . . . /. synchronizing the sync input must pass from a logic level low, through the maximum synchronization threshold with a duty cycle between 10% and 90%. the input can be driven directly from a logic level output. the synchronizing range is equal to initial operating frequency up to 700khz. this means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency (570khz), not the typical operating frequency of 500khz. caution should be used when synchronizing above 662khz because at higher sync frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. this type of subharmonic switching only occurs at input voltages less than twice output voltage. higher inductor values will tend to eliminate this problem. see frequency compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensa- tion. application note 19 has more details on the theory of slope compensation. at power-up, when v c is being clamped by the fb pin (see figure 2, q2), the sync function is disabled. this allows the frequency foldback to operate in the shorted output con- dition. during normal operation, switching frequency is controlled by the internal oscillator until the fb pin reaches 0.8v, after which the sync pin becomes operational. if no synchronization is required, this pin should be connected to ground. applicatio s i for atio wu uu + + 2.38v 0.4v gnd v sw lt1956 input r fb l1 r hi 1956 f04 output c1 shdn standby in total shutdown 5.5 m a r lo c2 + figure 4. undervoltage lockout
17 lt1956/lt1956-5 1956f applicatio s i for atio wu uu layout considerations as with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. for maximum efficiency, switch rise and fall times are typically in the nanosecond range. to prevent noise both radiated and conducted, the high speed switching current path, shown in figure 5, must be kept as short as possible. this is implemented in the suggested layout of figure 6. shorten- ing this path will also reduce the parasitic trace inductance of approximately 25nh/inch. at switch off, this parasitic inductance produces a flyback spike across the lt1956 switch. when operating at higher currents and input voltages, with poor layout, this spike can generate volt- ages across the lt1956 that may exceed its absolute maximum rating. a ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. the v c and fb components should be kept as far away as possible from the switch and boost nodes. the lt1956 pinout has been designed to aid in this. the ground for these components should be separated from the switch current path. failure to do so will result in poor stability or subharmonic like oscillation. figure 6. suggested layout gnd gnd shdn sync gnd boost v in sw place feedthrough around ground pins (4 corners) for good thermal conductivity lt1956 c3 c1 d1 c2 d2 r2 r1 1956 f06 c fb c f r c c c l1 minimize lt1956 c3-d1 loop gnd gnd bias fb v c connect to ground plane kelvin sense v out keep fb and v c components away from high frequency, high current components gnd v out v in for the fe package, solder the exposed pad to the copper ground plane underneath the device 1956 f05 5v l1 v in lt1956 d1 c1 c3 high frequency circulating path load figure 5. high speed switching path
18 lt1956/lt1956-5 1956f board layout also has a significant effect on thermal resis- tance. for the gn package, pins 1, 8, 9 and 16, gnd, are a continuous copper plate that runs under the lt1956 die. this is the best thermal path for heat out of the package. reducing the thermal resistance from pins 1, 8, 9 and 16 onto the board will reduce die temperature and increase the power capability of the lt1956. this is achieved by providing as much copper area as possible around these pins. adding multiple solder filled feedthroughs under and around these four corner pins to the ground plane will also help. similar treatment to the catch diode and coil termi- nations will reduce any additional heating effects. for the fe package, the exposed pad should be soldered to the copper ground plane underneath the device. parasitic resonance resonance or ringing may sometimes be seen on the switch node (see figure 7). very high frequency ringing following switch rise time is caused by switch/diode/input capacitor lead inductance and diode capacitance. schot- tky diodes have very high q junction capacitance that can ring for many cycles when excited at high frequency. if total lead length for the input capacitor, diode and switch path is 1 inch, the inductance will be approximately 25nh. at switch off, this will produce a spike across the npn output device in addition to the input voltage. at higher currents this spike can be in the order of 10v to 20v or higher with a poor layout, potentially exceeding the abso- lute max switch voltage. the path around switch, catch diode and input capacitor must be kept as short as possible to ensure reliable operation. when looking at this, applicatio s i for atio wu uu a >100mhz oscilloscope must be used, and waveforms should be observed on the leads of the package. this switch off spike will also cause the sw node to go below ground. the lt1956 has special circuitry inside which mitigates this problem, but negative voltages over 0.8v lasting longer than 10ns should be avoided. note that 100mhz oscilloscopes are barely fast enough to see the details of the falling edge overshoot in figure 7. a second, much lower frequency ringing is seen during switch off time if load current is low enough to allow the inductor current to fall to zero during part of the switch off time (see figure 8). switch and diode capacitance resonate with the inductor to form damped ringing at 1mhz to 10 mhz. this ringing is not harmful to the regulator and it has not been shown to contribute significantly to emi. any attempt to damp it with a resistive snubber will degrade efficiency. thermal calculations power dissipation in the lt1956 chip comes from four sources: switch dc loss, switch ac loss, boost circuit current, and input quiescent current. the following formu- las show how to calculate each of these losses. these formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. switch loss: p ri v v tivf sw sw out out in eff out in = ()( ) + ()()() 2 12 (/ ) figure 7. switch node resonance 50ns/div 1956 f07 2v/div sw rise sw fall switch node voltage inductor current at i out = 0.1a v in = 25v 500ns/div 1956 f08 v out = 5v l = 15 m h figure 8. discontinuous mode ringing 10v/div 0.2a/div
19 lt1956/lt1956-5 1956f applicatio s i for atio wu uu boost current loss: p vi v boost out out in = () 2 36 / quiescent current loss: pv v q in out = () + () 0 0015 0 003 .. r sw = switch resistance ( ? 0.3) hot t eff = effective switch current/voltage overlap time = (t r + t f + t ir + t if ) t r = (v in /1.2)ns t f = (v in /1.7)ns t ir = t if = (i out /0.05)ns f = switch frequency example: with v in = 12v, v out = 5v and i out = 1a: p w pw pw sw boost q = ()()() + () () ()( ) () =+= = () () = = () + () = - 03 1 5 12 57 10 1 2 1 12 500 10 0 125 0 171 0 296 5136 12 0 058 12 0 0015 5 0 003 0 033 2 93 2 . / ... / . ... total power dissipation in the ic is given by: p tot = p sw + p boost + p q = 0.296w + 0.058w + 0.033w = 0.39w thermal resistance for the lt1956 packages is influenced by the presence of internal or backside planes. ssop (gn16) package: with a full plane under the gn16 package, thermal resistance will be about 85 c/w. tssop (exposed pad) package: with a full plane under the tssop package, thermal resistance ( q ja ) will be about 45 c/w. to calculate die temperature, use the proper thermal resistance ( q ja ) number for the desired package an add in worst-case ambient temperature: t j = t a + ( q ja ? p tot ) when estimating ambient, remember the nearby catch diode and inductor will also be dissipating power. p vv v i v diode f in out load in = ( )( )( ) v f = forward voltage of diode (assume 0.63v at 1a) pw diode == (. )( )() . 063 12 5 1 12 037 notice that the catch diodes forward voltage contributes a significant loss in the overall system efficiency. a larger, low v f diode can improve efficiency by several percent. p inductor = (i load )(l dcr ) l dcr = inductor dc resistance (assume 0.1 w ) p inductor = (1)(0.1) = 0.1w typical thermal resistance of the board is 10 c/w. taking the catch diode and inductor power dissipation into ac- count and using the example calculations for lt1956 dis- sipation, the lt1956 die temperature will be estimated as: t j = t a + ( q ja ? p tot ) + (10 ? [p diode + p inductor ]) with the gn16 package ( q ja = 85 c/w), at an ambient temperature of 70 c: t j = 70 + (85 ? 0.39) + (10 ? 0.47) = 108 c with the tssop package ( q ja = 45 c/w) at an ambient temperature of 70 c: t j = 70 + (45 ? 0.37) + (10 ? 0.47) = 91 c die temperature can peak for certain combinations of v in , v out and load current. while higher v in gives greater switch ac losses, quiescent and catch diode losses, a lower v in may generate greater losses due to switch dc losses. in general, the maximum and minimum v in levels should be checked with maximum typical load current for calculation of the lt1956 die temperature. if a more accurate die temperature is required, a measurement of the sync pin resistance (to gnd) can be used. the sync pin resistance can be measured by forcing a voltage no greater than 0.5v at the pin and monitoring the pin current over temperature in a oven. this should be done with minimal device power (low v in and no switching [v c = 0v]) in order to calibrate sync pin resistance with ambient (oven) temperature.
20 lt1956/lt1956-5 1956f applicatio s i for atio wu uu note: some of the internal power dissipation in the ic, due to boost pin voltage, can be transferred outside of the ic to reduce junction temperature by increasing the voltage drop in the path of the boost diode d2 (see figure 9). this reduction of junction temperature inside the ic will allow higher ambient temperature operation for a given set of conditions. boost pin circuitry dissipates power given by: p vi v v diss out sw c in (boost pin) = () / 36 2 typically, v c2 (the boost voltage across the capacitor c2) equals v out . this is because diodes d1 and d2 can be considered almost equal, where: v c2 = v out C v f (d2) C [Cv f (d1)] = v out . hence, the equation for boost circuitry power dissipation given in the previous thermal calculations section, is stated as: p vi v v diss boost out sw out in () / = () 36 here it can be seen that boost power dissipation increases as the square of v out . it is possible, however, to reduce v c2 below v out to save power dissipation by increasing the voltage drop in the path of d2. care should be taken that v c2 does not fall below the minimum 3.3v boost voltage required for full saturation of the internal power switch. for output voltages of 5v, v c2 is approximately 5v. during switch turn on, v c2 will fall as the boost capacitor c2 is discharged by the boost pin. in the previous boost pin section, the value of c2 was designed for a 0.7v droop in v c2 (= v droop ). hence, an output voltage as low as 4v would still allow the minimum 3.3v for the boost function using the c2 capacitor calculated. if a target output voltage of 12v is required, however, an excess of 8v is placed across the boost capacitor which is not required for the boost function but still dissipates additional power. what is required is a voltage drop in the path of d2 to achieve minimal power dissipation while still maintaining minimum boost voltage across c2. a zener, d4, placed in series with d2 (see figure 9), drops voltage to c2. example: the boost pin power dissipation for a 20v input to 12v output conversion at 1a is given by: pw boost = () = 12 1 36 12 20 02 / . if a 7v zener is placed in series with d2, then power dissipation becomes: pw boost = () = 12 1 36 5 20 0 084 / . for an fe package with thermal resistance of 45 c/w, ambient temperature savings would be: t (ambient) savings = 0.116w ? 45 c/w = 5 c for a gn package with thermal resistance of 85 c/w, ambient temperature savings would be: t (ambient) savings = 0.116w ? 85 c/w = 10 c the 7v zener should be sized for excess of 0.116w operation. the tolerances of the zener should be consid- ered to ensure minimum v boost exceeds 3.3v + v droop . boost v in d1 r1 v out c f c c lt1956 shdn sync sw bias fb v c gnd c2 c1 l1 d2 r c r2 1956 f09 c3 v in d2 d4 + figure 9. boost pin, diode selection
21 lt1956/lt1956-5 1956f applicatio s i for atio wu uu input voltage vs operating frequency considerations the absolute maximum input supply voltage for the lt1956 is specified at 60v. this is based on internal semiconduc- tor junction breakdown effects. the practical maximum input supply voltage for the lt1956 may be less than 60v due to internal power dissipation or switch minimum on time considerations. for the extreme case of an output short-circuit fault to ground, see the section short-circuit considerations. a detailed theoretical basis for estimating internal power dissipation is given in the thermal calculations section. this will allow a first pass check of whether an applications maximum input voltage requirement is suitable for the lt1956. be aware that these calculations are for dc input voltages and that input voltage transients as high as 60v are possible if the resulting increase in internal power dissipation is of insufficient time duration to raise die temperature significantly. for the fe package, this means high voltage transients on the order of hundreds of milli- seconds are possible. if lt1956 (fe package) thermal calculations show power dissipation is not suitable for the given application, the lt1766 (fe package) is a recom- mended alternative since it is identical to the lt1956 but runs cooler at 200khz. switch minimum on time is the other factor that may limit the maximum operational input voltage for the lt1956 if pulse-skipping behavior is not allowed. for the lt1956, pulse-skipping may occur for v in /(v out + v f ) ratios > 4. (v f = schottky diode d1 forward voltage drop, figure 5.) if the lt1766 is used, the ratio increases to 10. pulse- skipping is the regulators way of missing switch pulses to maintain output voltage regulation. although an increase in output ripple voltage can occur during pulse-skipping, a ceramic output capacitor can be used to keep ripple voltage to a minimum (see output ripple voltage compari- son for tantalum vs ceramic output capacitors, figure 3). frequency compensation before starting on the theoretical analysis of frequency response, the following should be rememberedthe worse the board layout, the more difficult the circuit will be to stabilize. this is true of almost all high frequency analog circuits, read the layout considerations section first. common layout errors that appear as stability problems are distant placement of input decoupling capacitor and/ or catch diode, and connecting the v c compensation to a ground track carrying significant switch current. in addi- tion, the theoretical analysis considers only first order non-ideal component behavior. for these reasons, it is important that a final stability check is made with produc- tion layout and components. the lt1956 uses current mode control. this alleviates many of the phase shift problems associated with the inductor. the basic regulator loop is shown in figure 10. the lt1956 can be considered as two g m blocks, the error amplifier and the power stage. figure 11 shows the overall loop response. at the v c pin, the frequency compensation components used are: r c = 2.2k, c c = 0.022 m f and c f = 220pf. the output capacitor used is a 100 m f, 10v tantalum capacitor with typical esr of 100m w . the esr of the tantalum output capacitor provides a useful zero in the loop frequency response for maintaining stabil- ity. this esr, however, contributes significantly to the ripple voltage at the output (see output ripple voltage in the applications information section). it is possible to reduce capacitor size and output ripple voltage by replac- ing the tantalum output capacitor with a ceramic output capacitor because of its very low esr. the zero provided by the tantalum output capacitor must now be reinserted back into the loop. alternatively, there may be cases where, even with the tantalum output capacitor, an addi- tional zero is required in the loop to increase phase margin for improved transient response. a zero can be added into the loop by placing a resistor (r c ) at the v c pin in series with the compensation capacitor, c c , or by placing a capacitor (c fb ) between the output and the fb pin. when using r c , the maximum value has two limitations. first, the combination of output capacitor esr and r c may stop the loop rolling off altogether. second, if the loop gain is not rolled off sufficiently at the switching frequency, output ripple will perturb the v c pin enough to cause unstable duty cycle switching similar to subharmonic
22 lt1956/lt1956-5 1956f applicatio s i for atio wu uu oscillations. if needed, an additional capacitor (c f ) can be added across the r c /c c network from the v c pin to ground to further suppress v c ripple voltage. with a tantalum output capacitor, the lt1956 already includes a resistor (r c ) and filter capacitor (c f ) at the v c pin (see figures 10 and 11) to compensate the loop over the entire v in range (to allow for stable pulse skipping for high v in -to-v out ratios 3 4). a ceramic output capacitor can still be used with a simple adjustment to the resistor r c for stable operation (see ceramic capacitors section for stabilizing lt1956). if additional phase margin is required, a capacitor (c fb ) can be inserted between the output and fb pin but care must be taken for high output voltage applications. sudden shorts to the output can create unacceptably large negative transients on the fb pin. for v in -to-v out ratios < 4, higher loop bandwidths are possible by readjusting the frequency compensation com- ponents at the v c pin. when checking loop stability, the circuit should be oper- ated over the applications full voltage, current and tem- perature range. proper loop compensation may be obtained by empirical methods as described in application notes 19 and 76. converter with backup output regulator in systems with a primary and backup supply, for ex- ample, a battery powered device with a wall adapter input, the output of the lt1956 can be held up by the backup supply with the lt1956 input disconnected. in this condi- tion, the sw pin will source current into the v in pin. if the shdn pin is held at ground, only the shut down current of 25 m a will be pulled via the sw pin from the second supply. with the shdn pin floating, the lt1956 will consume its quiescent operating current of 1.5ma. the v in pin will also source current to any other components connected to the input line. if this load is greater than 10ma or the input could be shorted to ground, a series schottky diode must be added, as shown in figure 12. with these safeguards, the output can be held at voltages up to the v in absolute maximum rating. buck converter with adjustable soft-start large capacitive loads or high input voltages can cause high input currents at start-up. figure 13 shows a circuit that limits the dv/dt of the output at start-up, controlling the capacitor charge rate. the buck converter is a typical configuration with the addition of r3, r4, c ss and q1. as the output starts to rise, q1 turns on, regulating switch frequency (hz) gain (db) 80 60 40 20 0 ?0 ?0 phase (deg) 180 150 120 90 60 30 0 1956 f11 gain phase 10 v in = 12v v out = 5v i load = 500ma c out = 100 f, 10v, 0.1 1k 10k 1m 100 100k r c = 2.2k c c = 22nf c f = 220pf + 1.22v sw v c lt1956 gnd 1956 f10 r1 output esr c f c c r c r o 200k error amplifier fb r2 c1 r load current mode power stage g m = 2mho g m = 2000 mho + tantalum esl c1 ceramic c fb figure 10. model for loop response figure 11. overall loop response
23 lt1956/lt1956-5 1956f applicatio s i for atio wu uu current via the v c pin to maintain a constant dv/dt at the output. output rise time is controlled by the current through c ss defined by r4 and q1s v be . once the output is in regulation, q1 turns off and the circuit operates normally. r3 is transient protection for the base of q1. risetime rc v v ss out be = ()( )( ) 4 using the values shown in figure 10, rise time ms = ()( ) () = 47 10 15 10 5 07 5 39 . the ramp is linear and rise times in the order of 100ms are possible. since the circuit is voltage controlled, the ramp rate is unaffected by load characteristics and maximum output current is unchanged. variants of this circuit can be used for sequencing multiple regulator outputs. dual polarity output converter the circuit in figure 14a generates both positive and negative 5v outputs with all components under 3mm height. the topology for the 5v output is a standard buck converter. the C5v output uses a second inductor l2, diode d3 and output capacitor c6. the capacitor c4 5v, 1a removable input c2 0.1 m f c f 220pf r c 2.2k r3 54k d1 10mq060n 1956 f12 c3 2.2 m f d3 10mq060n mmsd914ti l1 18 m h c c 0.022 f c1 100 f 10v alternate supply r4 25k r1 15.4k r2 4.99k boost v in lt1956 shdn sync sw bias fb v c gnd + figure 12. dual source supply with 25 m a reverse leakage output 5v 1a input 12v 1766 f13 c2 0.1 m f c1 100 m f c ss 15nf d1 c3 2.2 m f ceramic d2 mmsd914ti l1 18 m h r1 15.4k r3 2k r2 4.99k r4 47k q1 r c 2.2k c f 220pf c c 0.022 f boost bias v in lt1956 shdn sync sw fb v c gnd + figure 13. buck converter with adjustable soft-start
24 lt1956/lt1956-5 1956f couples energy to l2 and ensures equal voltages across l2 and l1 during steady state. instead of using a trans- former for l1 and l2, uncoupled inductors were used because they require less height than a single transformer, can be placed separately in the circuit layout for optimized space savings and reduce overall cost. this is true even when the uncoupled inductors are sized (twice the value of inductance of the transformer) in order to keep ripple current comparable to the transformer solution. if a single transformer becomes available to provide a better height/ cost solution, refer to the dual output sepic circuit de- scription in design note 100 for correct transformer connection. during switch on-time, in steady state, the voltage across both l1 and l2 is positive and equal; with energy (and current) ramping up in each inductor. the current in l2 is provided by the coupling capacitor c4. during switch off- time, current ramps downward in each inductor. the applicatio s i for atio wu uu v out1 ** 5v v out2 ** ? ?v *sumida cdrh4d28-150 **see figure 14c for v out1 , v out2 load current relationship ? if load can go to zero, an optional preload of 500 can be used to improve regulation v in 9v to 12v (transients to 36v) gnd 1956 f14a c2 0.1 m f c f 220pf r c 2.2k d1 b0540w c5 10 m f 6.3v cer c6 10 m f 6.3v cer c3 2.2 m f 50v ceramic c4 10 f 6.3v cer d2 mmsd914ti d3 b0540w l1* 15 m h l2* c c 3300pf r1 15.4k r2 4.99k + + + boost v in lt1956 shdn sync sw fb v c gnd figure 14a. dual polarity output converter v out1 load current (ma) 0 0 v out2 maximum load current (ma) 50 150 200 250 500 350 200 400 1956 f15b 100 400 450 300 600 800 figure 14b. v out2 (C5v) maximum allowable load current vs v out1 (5v) load current v out2 load current (ma) 0 4.75 |v out2 | (v) 4.85 4.95 5.05 5.15 100 200 300 400 1956 f14c 500 600 5.25 4.80 4.90 5.00 5.10 5.20 5.30 v out1 load current 750ma v out1 load current 250ma v out1 load current 500ma v out2 load current (ma) 0 efficiency (%) 60 80 100 400 1956 f14d 40 20 50 70 90 30 10 0 100 200 300 500 v out1 load current 750ma v out1 load current 250ma figure 14c. v out2 (C5v) output voltage vs load current figure 14d. dual polarity output converter efficiency
25 lt1956/lt1956-5 1956f current in l2 and c4 flows via the catch diode d3, charging the negative output capacitor c6. if the negative output is not loaded enough, it can go severely unregulated (be- come more negative). figure 14b shows the maximum allowable C5v output load current (vs load current on the 5v output) that will maintain the C5v output within 3% tolerance. figure 14c shows the C5v output voltage regu- lation vs its own load current when plotted for three separate load currents on the 5v output. the efficiency of the dual output converter circuit shown in figure 14a is given in figure 14d. positive-to-negative converter the circuit in figure 15 is a positive-to-negative topology using a grounded inductor. it differs from the standard approach in the way the ic chip derives its feedback signal because the lt1956 accepts only positive feedback sig- nals. the ground pin must be tied to the regulated negative output. a resistor divider to the fb pin, then provides the proper feedback voltage for the chip. the following equation can be used to calculate maximum load current for the positive-to-negative converter: applicatio s i for atio wu uu i i vv vvfl vv vv vv max p in out out in out in out in out f = + ? ? ++ ()( ) ()()() ()(.) (.)() 2 03 03 i p = maximum rated switch current v in = minimum input voltage v out = output voltage v f = catch diode forward voltage 0.3 = switch voltage drop at 1.5a example: with v in(min) = 5.5v, v out = 12v, l = 15 m h, v f = 0.63v, i p = 1.5a: i max = 0.36a. inductor value the criteria for choosing the inductor is typically based on ensuring that peak switch current rating is not exceeded. this gives the lowest value of inductance that can be used, but in some cases (lower output load currents) it may give a value that creates unnecessarily high output ripple voltage. the difficulty in calculating the minimum inductor size needed is that you must first decide whether the switcher will be in continuous or discontinuous mode at the critical point where switch current reaches 1.5a. the first step is to use the following formula to calculate the load current above which the switcher must use continuous mode. if your load current is less than this, use the discontinuous mode formula to calculate minimum inductor needed. if load current is higher, use the continuous mode formula. output current where continuous mode is needed: i vi vv vv v cont in p in out in out f > +++ ()() ()( ) 22 4 minimum inductor discontinuous mode: l vi fi min out out p = 2 2 ()() ()( ) output** ?2v, 0.25a v in 12v 1956 f15 c2 0.1 m f c c r c d1 10mqo60n r1 36.5k c1 100 m f 20v tant c3 2.2 f 25v d2 mmsd914ti l1* 7 m h c f boost lt1956 v in sw fb gnd v c r2 4.12k * increase l1 to 10 m h or 18 m h for higher current applications. see applications information ** maximum load current depends on minimum input voltage and inductor size. see applications information + figure 15. positive-to-negative converter
26 lt1956/lt1956-5 1956f u package descriptio minimum inductor continuous mode: l vv fv v i i vv v min in out in out p out out f in = ++ + ? ? ? ? ? ? ()( ) ()( ) () 21 for a 12v to C12v converter using the lt1956 with peak switch current of 1.5a and a catch diode of 0.63v: ia cont > +++ = ()(.) ()( .) . 12 1 5 412121212063 0 370 22 for a load current of 0.25a, this says that discontinuous mode can be used and the minimum inductor needed is found from: lh min ==m 212 025 500 10 1 5 53 32 ()(.) ()(.) . in practice, the inductor should be increased by about 30% over the calculated minimum to handle losses and variations in value. this suggests a minimum inductor of 7 m h for this application. ripple current in the input and output capacitors positive-to-negative converters have high ripple current in the input capacitor. for long capacitor lifetime, the rms value of this current must be less than the high frequency ripple current rating of the capacitor. the following formula will give an approximate value for rms ripple current. this formula assumes continuous mode and large inductor value . small inductors will give some- what higher ripple current, especially in discontinuous mode. the exact formulas are very complex and appear in application note 44, pages 29 and 30. for our pur- poses here i have simply added a fudge factor (ff). the value for ff is about 1.2 for higher load currents and l 3 15 m h. it increases to about 2.0 for smaller inductors at lower load currents. capacitor i ff i v v rms out out in = ()( ) ff = 1.2 to 2.0 the output capacitor ripple current for the positive-to- negative converter is similar to that for a typical buck regulatorit is a triangular waveform with peak-to-peak value equal to the peak-to-peak triangular waveform of the inductor. the low output ripple design in figure 14 places the input capacitor between v in and the regulated negative output. this placement of the input capacitor significantly reduces the size required for the output capacitor (versus placing the input capacitor between v in and ground). the peak-to-peak ripple current in both the inductor and output capacitor (assuming continuous mode) is: i p-p p-p = == + ++ = dc v fl dc duty cycle vv vvv i rms i in out f out in f cout () 12 the output ripple voltage for this configuration is as low as the typical buck regulator based predominantly on the inductors triangular peak-to-peak ripple current and the esr of the chosen capacitor (see output ripple voltage in applications information). diode current average diode current is equal to load current. peak diode current will be considerably higher. peak diode current: continuous mode i vv v vv lfv v discontinuous mode iv lf out in out in in out in out out out = + + + = ()()() ()()( ) ()( ) ()() 2 2 keep in mind that during start-up and output overloads, average diode current may be much higher than with normal loads. care should be used if diodes rated less than 1a are used, especially if continuous overload conditions must be tolerated.
27 lt1956/lt1956-5 1956f u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bb fe16 (bb) tssop 0203 0.09 ?0.20 (.0036 ?.0079) 0 ?8 0.45 ?0.75 (.018 ?.030) 4.30 ?4.50* (.169 ?.177) 6.40 bsc 134 5 6 7 8 10 9 4.90 ?5.10* (.193 ?.201) 16 1514 13 12 11 1.10 (.0433) max 0.05 ?0.15 (.002 ?.006) 0.65 (.0256) bsc 2.94 (.116) 0.195 ?0.30 (.0077 ?.0118) 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment
28 lt1956/lt1956-5 1956f lt/tp 0303 2k ? printed in usa ? linear technology corporation 2001 related parts part number description comments lt1074/lt1076/ step-down switching regulators up to 64v input, 100khz, 5a and 2a lt1076hv lt1082 1a high voltage/efficiency switching voltage regulator up to 75v input, 60khz operation lt1370 high efficiency dc/dc converter up to 42v, 6a, 500khz switch lt1371 high efficiency dc/dc converter up to 35v, 3a, 500khz switch lt1375/lt1376 1.5a, 500khz step-down switching regulators operation up to 25v input, synchronizable (lt1375), n8, s8, s16 lt1616 600ma, 1.4mhz step-down switching regulator 3.6v to 25v v in , 6-lead thinsot tm lt1676 wide input range, high efficiency, step-down switching regulator 7.4v to 60v v in , 100khz operation, 700ma internal switch, s8 lt1765 monolithic 3a, 1.25mhz step-down regulator v in : 3v to 25v; v ref = 1.2v; s8, tssop-16e exposed pad lt1766 wide input range, high efficiency, step-down switching regulator 5.5v to 60v input, 200khz operation, 1.5a internal switch , tssop-16e lt1767 monolithic 1.5a, 1.25mhz step-down regulator v in : 3v to 25v; v ref = 1.2v; ms8 lt1776 wide input range, high efficiency, step-down switching regulator up to 7.4v to 60v, 200khz operation, 700ma internal switc h, tssop-16e lt1777 low noise buck regulator operation up to 48v, controlled voltage and current slew rates, s16 thinsot is a trademark of linear technology corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale u package descriptio

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